1. Field of the Invention
The present invention relates to a memory circuit, and more particularly, to a memory circuit and a method for controlling the memory circuit which can reduce leakage current.
2. Description of the Prior Art
Please refer to FIG. 1, which is a diagram illustrating a prior art SRAM (Static Random Access Memory) unit 100. As shown in FIG. 1, the SRAM unit 100 includes six transistors N1-N4 and P1-P2, and data can be written into or read from the SRAM unit 100 by switching voltage levels of a word line WL, a bit line BL and a complementary bit line BL. Because a person skilled in this art should understand the operations of the SRAM unit 100, further descriptions are omitted here.
Still referring to FIG. 1, when the SRAM unit 100 is operated under an inactive mode (i.e., the transistors N3 and N4 are switched off), voltage levels of the nodes A and B will be shifted due to the leakage current, and a reading error may occur when reading data from the SRAM unit 100. For example, assuming that the SRAM 100 is operated under the inactive mode and the voltage levels of the nodes A and B are VDD and VSS, respectively, there are two leakage current paths that exist between the node A and a supply voltage source VSS, which are, respectively, a sub-threshold leakage current generated by the transistor N1 and a gate leakage current generated by the transistor N2. Similarly, there are two leakage current paths that exist between the node B and a supply voltage source VDD, which are, respectively, a sub-threshold leakage current generated by the transistor P2 and a gate leakage current generated by the transistor P1. In addition, in deep sub-micro processes, these leakage currents will be increased exponentially, and may even become a main power consumption of the integrated circuit.
In order to solve the above-mentioned leakage current issue of the SRAM unit 100, U.S. Pat. No. 7,110,317 discloses a technique which can reduce the leakage current. Referring to the SRAM unit 501 shown in FIG. 2 of the U.S. Pat. No. 7,110,317, transistors P1 and P2 are connected to a supply voltage source VDD via a bias circuit 510 including transistors 511-513, and transistors N1 and N2 are connected to a supply voltage source VSS via a bias circuit 520 including transistors 521-523. When the SRAM unit 501 is operated under the inactive mode, the actual supply voltages of the SRAM unit 501 are (VDD−Vth) and (VSS+Vth), where Vth is a threshold voltage of the transistors 512-513 and 522-523. Therefore, the leakage current of the SRAM unit 501 can be effectively reduced because of a lower potential difference between the nodes A, B and the actual supply voltages. However, the threshold voltage of the transistors may be shifted due to variations of process, voltage and temperature (PVT), thereby influencing the supply voltages levels of the SRAM unit 501 when operated in the inactive mode, and causing data loss in the SRAM unit 501.
In addition, U.S. Pat. No. 5,581,500 also discloses a technique to reduce the leakage current. Referring to the SRAM unit 10 shown in FIG. 3 of U.S. Pat. No. 5,581,500, the SRAM unit 10 includes a (VSS+Δ) generator 30. When the SRAM unit 10 is operated under the inactive mode, a voltage level of a node A shown in FIG. 3 is (VSS+Δ). This means the leakage current can be improved because a voltage difference between the node A and nodes of the inverters 12 and 14 having a higher voltage is lowered. However, an SRAM array using the technique of U.S. Pat. No. 5,581,500 requires a higher manufacturing cost because each row of the SRAM array needs a (VSS+Δ) generator 30. Furthermore, the (VSS+Δ) generator 30 itself may have the leakage current.